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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-12 00:46:09 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-12 00:46:09 +0200 |
| commit | 7bcf7717b6a047c272410d0cd00213185fe6b99d (patch) | |
| tree | 81c5d6bbc2130815713e22bb5408ea80b6e1c499 /arch/mips/configs/bigsur_defconfig | |
| parent | [MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers. (diff) | |
| download | linux-7bcf7717b6a047c272410d0cd00213185fe6b99d.tar.xz linux-7bcf7717b6a047c272410d0cd00213185fe6b99d.zip | |
[MIPS] Implement clockevents for R4000-style cp0 count/compare interrupt
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/configs/bigsur_defconfig')
| -rw-r--r-- | arch/mips/configs/bigsur_defconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 700a3a2d688e..30f3e9a2466f 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -69,7 +69,6 @@ CONFIG_SIBYTE_SB1xxx_SOC=y CONFIG_SIBYTE_CFE=y # CONFIG_SIBYTE_CFE_CONSOLE is not set # CONFIG_SIBYTE_BUS_WATCHER is not set -# CONFIG_SIBYTE_SB1250_PROF is not set # CONFIG_SIBYTE_TBPROF is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set |