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| author | Julia Lawall <Julia.Lawall@inria.fr> | 2022-04-30 21:03:10 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2022-05-04 22:22:59 +0200 |
| commit | 94bd83e45acdd72b81545ff25324a13bc5cae54e (patch) | |
| tree | 3f5d2f5e98d180d44794feb43cb3f1d9418b8200 /arch/mips/dec/ioasic-irq.c | |
| parent | mips: dts: ingenic: x1000: Add PWM device tree node (diff) | |
| download | linux-94bd83e45acdd72b81545ff25324a13bc5cae54e.tar.xz linux-94bd83e45acdd72b81545ff25324a13bc5cae54e.zip | |
MIPS: fix typos in comments
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/dec/ioasic-irq.c')
| -rw-r--r-- | arch/mips/dec/ioasic-irq.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index 130eb67bd3c9..971f7b46759b 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -68,13 +68,13 @@ static struct irq_chip ioasic_dma_irq_type = { * I/O ASIC implements two kinds of DMA interrupts, informational and * error interrupts. * - * The formers do not stop DMA and should be cleared as soon as possible + * The former do not stop DMA and should be cleared as soon as possible * so that if they retrigger before the handler has completed, usually as * a side effect of actions taken by the handler, then they are reissued. * These use the `handle_edge_irq' handler that clears the request right * away. * - * The latters stop DMA and do not resume it until the interrupt has been + * The latter stop DMA and do not resume it until the interrupt has been * cleared. This cannot be done until after a corrective action has been * taken and this also means they will not retrigger. Therefore they use * the `handle_fasteoi_irq' handler that only clears the request on the |