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| author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2006-06-20 16:55:17 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-06-29 22:10:52 +0200 |
| commit | 6feb6efaec9858dfb673fc5c89b8280b1b73bb08 (patch) | |
| tree | 47f4c175589cbb5bcdcf826be5e078b3c97edabc /arch/mips/gt64120 | |
| parent | [MIPS] Fix configuration of R2 CPU features and multithreading. (diff) | |
| download | linux-6feb6efaec9858dfb673fc5c89b8280b1b73bb08.tar.xz linux-6feb6efaec9858dfb673fc5c89b8280b1b73bb08.zip | |
[MIPS] Remove first timer interrupt setup in wrppmc_timer_setup()
The first timer interrupt setup already happens in time_init().
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/gt64120')
| -rw-r--r-- | arch/mips/gt64120/wrppmc/time.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index 175d22adb450..6c24a82df0dd 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c @@ -31,10 +31,6 @@ void __init wrppmc_timer_setup(struct irqaction *irq) { /* Install ISR for timer interrupt */ setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); - - /* to generate the first timer interrupt */ - write_c0_compare(mips_hpt_frequency/HZ); - write_c0_count(0); } /* |