diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 18:17:33 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 18:17:33 +0200 |
| commit | ade63aada79c61bcd5f51cbd310f237399892268 (patch) | |
| tree | 4f8605528bfd9b6261679883974b9ac4870223dd /arch/mips/include/asm/asmmacro.h | |
| parent | MIPS: CPC: Use __raw_ memory access functions (diff) | |
| parent | MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume() (diff) | |
| download | linux-ade63aada79c61bcd5f51cbd310f237399892268.tar.xz linux-ade63aada79c61bcd5f51cbd310f237399892268.zip | |
Merge branch '3.14-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm/asmmacro.h')
| -rw-r--r-- | arch/mips/include/asm/asmmacro.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index fe3b03c793e5..b464b8b1147a 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -9,6 +9,7 @@ #define _ASM_ASMMACRO_H #include <asm/hazards.h> +#include <asm/asm-offsets.h> #ifdef CONFIG_32BIT #include <asm/asmmacro-32.h> @@ -54,11 +55,21 @@ .endm .macro local_irq_disable reg=t0 +#ifdef CONFIG_PREEMPT + lw \reg, TI_PRE_COUNT($28) + addi \reg, \reg, 1 + sw \reg, TI_PRE_COUNT($28) +#endif mfc0 \reg, CP0_STATUS ori \reg, \reg, 1 xori \reg, \reg, 1 mtc0 \reg, CP0_STATUS irq_disable_hazard +#ifdef CONFIG_PREEMPT + lw \reg, TI_PRE_COUNT($28) + addi \reg, \reg, -1 + sw \reg, TI_PRE_COUNT($28) +#endif .endm #endif /* CONFIG_MIPS_MT_SMTC */ @@ -106,7 +117,7 @@ .endm .macro fpu_save_double thread status tmp -#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) sll \tmp, \status, 5 bgez \tmp, 10f fpu_save_16odd \thread @@ -159,7 +170,7 @@ .endm .macro fpu_restore_double thread status tmp -#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) sll \tmp, \status, 5 bgez \tmp, 10f # 16 register mode? |