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authorRalf Baechle <ralf@linux-mips.org>2011-06-17 17:20:28 +0200
committerRalf Baechle <ralf@linux-mips.org>2011-10-20 16:00:18 +0200
commitd9cdc901af0f92da7f90c750d8c187f5500be067 (patch)
tree1b5e11202d86081253ab1422e302b45902a346a3 /arch/mips/include/asm/cacheflush.h
parentMIPS: Lantiq: Fix MTD registration of NOR device (diff)
downloadlinux-d9cdc901af0f92da7f90c750d8c187f5500be067.tar.xz
linux-d9cdc901af0f92da7f90c750d8c187f5500be067.zip
MIPS: cache: Provide cache flush operations for XFS
Until now flush_kernel_vmap_range() and invalidate_kernel_vmap_range() did not exist on MIPS resulting in heavy cache corruption on XFS filesystems. Left for the post-3.0 time: optimization and make this work with highmem, too. Since the combination of highmem + cache aliases atm doesn't work this isn't a regression. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2505/
Diffstat (limited to 'arch/mips/include/asm/cacheflush.h')
-rw-r--r--arch/mips/include/asm/cacheflush.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 40bb9fde205f..69468ded2828 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -114,4 +114,28 @@ unsigned long run_uncached(void *func);
extern void *kmap_coherent(struct page *page, unsigned long addr);
extern void kunmap_coherent(void);
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+ BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
+}
+
+/*
+ * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
+ * cache writeback and invalidate operation.
+ */
+extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
+
+static inline void flush_kernel_vmap_range(void *vaddr, int size)
+{
+ if (cpu_has_dc_aliases)
+ __flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
+{
+ if (cpu_has_dc_aliases)
+ __flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
#endif /* _ASM_CACHEFLUSH_H */