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| author | Huacai Chen <chenhc@lemote.com> | 2016-03-03 02:45:11 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 14:02:14 +0200 |
| commit | 06e4814eec988f7ee01c29762f945b3ff59355fb (patch) | |
| tree | d23c5f9cf1b096b3bc67f458a6b0984b664d7cbf /arch/mips/include/asm/cpu-features.h | |
| parent | MIPS: Loongson-3: Set cache flush handlers to cache_noop (diff) | |
| download | linux-06e4814eec988f7ee01c29762f945b3ff59355fb.tar.xz linux-06e4814eec988f7ee01c29762f945b3ff59355fb.zip | |
MIPS: Loongson: Invalidate special TLBs when needed
Loongson-2 has a 4 entry itlb which is a subset of jtlb, Loongson-3 has
a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. We should
write diag register to invalidate itlb/dtlb when flushing jtlb because
itlb/dtlb are not totally transparent to software.
For Loongson-3A R2 (and newer), we should invalidate ITLB, DTLB, VTLB
and FTLB before we enable/disable FTLB.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
0 files changed, 0 insertions, 0 deletions