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| author | James Hogan <james.hogan@imgtec.com> | 2016-05-11 14:50:52 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:30:25 +0200 |
| commit | f18bdfa191df3947879f93519ce4a4985e5f5fce (patch) | |
| tree | cd76367f5217d0c81d43af9b1d451a54dd6faf59 /arch/mips/include/asm/cpu.h | |
| parent | MIPS: Add defs & probing of BadInstr[P] registers (diff) | |
| download | linux-f18bdfa191df3947879f93519ce4a4985e5f5fce.tar.xz linux-f18bdfa191df3947879f93519ce4a4985e5f5fce.zip | |
MIPS: Add defs & probing of [X]ContextConfig
The CP0_[X]ContextConfig registers are present if CP0_Config3.CTXTC or
CP0_Config3.SM are set, and provide more control over which bits of
CP0_[X]Context are set to the faulting virtual address on a TLB
exception.
KVM/VZ will need to be able to save and restore these registers in the
guest context, so add the relevant definitions and probing of the
ContextConfig feature in the root context first.
[ralf@linux-mips.org: resolve merge conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13225/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 0cf90d67c1af..ddcb2abd44ba 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -407,6 +407,7 @@ enum cpu_type_enum { #define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */ #define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ #define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ +#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */ /* * CPU ASE encodings |