diff options
| author | Yang Ling <gnaygnil@gmail.com> | 2016-05-19 06:22:19 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-10-04 16:13:57 +0200 |
| commit | a1ca83869d4ea65afd5a6a403d5d5ec2c41ef60e (patch) | |
| tree | 5803546b32133f709de02942cb031850b0e4455a /arch/mips/include/asm/cpu.h | |
| parent | MIPS: Octeon: Rename upper case variables at setup time. (diff) | |
| download | linux-a1ca83869d4ea65afd5a6a403d5d5ec2c41ef60e.tar.xz linux-a1ca83869d4ea65afd5a6a403d5d5ec2c41ef60e.zip | |
MIPS: Add CPU support for Loongson1C
Loongson1C is a 32-bit SoC designed by Loongson Technology Co., Ltd,
with many features similar to Loongson1B.
Signed-off-by: Yang Ling <gnaygnil@gmail.com>
Cc: paul.burton@imgtec.com
Cc: markos.chandras@imgtec.com
Cc: james.hogan@imgtec.com
Cc: kumba@gentoo.org
Cc: macro@imgtec.com
Cc: david.daney@cavium.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13303/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f672df8b26d0..9a8372484edc 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -240,6 +240,7 @@ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 #define PRID_REV_LOONGSON1B 0x0020 +#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON3A_R1 0x0005 |