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authorPaul Burton <paul.burton@imgtec.com>2016-10-05 19:18:16 +0200
committerRalf Baechle <ralf@linux-mips.org>2016-10-06 18:02:01 +0200
commit20d330645cfb8cfecfb82b369e4d3084e429e68a (patch)
treec2e0661dbbb76ad83b2645db4291954bbd19c69d /arch/mips/include/asm/device.h
parentMIPS: dma-default: Don't check hw_coherentio if device is non-coherent (diff)
downloadlinux-20d330645cfb8cfecfb82b369e4d3084e429e68a.tar.xz
linux-20d330645cfb8cfecfb82b369e4d3084e429e68a.zip
MIPS: Support per-device DMA coherence
On some MIPS systems, a subset of devices may have DMA coherent with CPU caches. For example in systems including a MIPS I/O Coherence Unit (IOCU), some devices may be connected to that IOCU whilst others are not. Prior to this patch, we have a plat_device_is_coherent() function but no implementation which does anything besides return a global true or false, optionally chosen at runtime. For devices such as those described above this is insufficient. Fix this by tracking DMA coherence on a per-device basis with a dma_coherent field in struct dev_archdata. Setting this from arch_setup_dma_ops() takes care of devices which set the dma-coherent property via device tree, and any PCI devices beneath a bridge described in DT, automatically. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14349/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/device.h')
-rw-r--r--arch/mips/include/asm/device.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index c94fafba9e62..21c2082a0dfb 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -11,6 +11,11 @@ struct dma_map_ops;
struct dev_archdata {
/* DMA operations on that device */
struct dma_map_ops *dma_ops;
+
+#ifdef CONFIG_DMA_PERDEV_COHERENT
+ /* Non-zero if DMA is coherent with CPU caches */
+ bool dma_coherent;
+#endif
};
struct pdev_archdata {