MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 83 insertions, 83 deletions

diff --git a/arch/mips/include/asm/jazz.h b/arch/mips/include/asm/jazz.h
index 83f449dec95e..a61970d01a81 100644
--- a/arch/mips/include/asm/jazz.h
+++ b/arch/mips/include/asm/jazz.h
@@ -16,7 +16,7 @@
  * instead of 0xe0000000.
  */
 
-#define JAZZ_LOCAL_IO_SPACE     0xe0000000
+#define JAZZ_LOCAL_IO_SPACE	0xe0000000
 
 /*
  * Revision numbers in PICA_ASIC_REVISION
@@ -25,24 +25,24 @@
  * 0xf0000001 - Rev2
  * 0xf0000002 - Rev3
  */
-#define PICA_ASIC_REVISION      0xe0000008
+#define PICA_ASIC_REVISION	0xe0000008
 
 /*
  * The segments of the seven segment LED are mapped
  * to the control bits as follows:
  *
- *         (7)
- *      ---------
- *      |       |
- *  (2) |       | (6)
- *      |  (1)  |
- *      ---------
- *      |       |
- *  (3) |       | (5)
- *      |  (4)  |
- *      --------- . (0)
+ *	   (7)
+ *	---------
+ *	|	|
+ *  (2) |	| (6)
+ *	|  (1)	|
+ *	---------
+ *	|	|
+ *  (3) |	| (5)
+ *	|  (4)	|
+ *	--------- . (0)
  */
-#define PICA_LED                0xe000f000
+#define PICA_LED		0xe000f000
 
 /*
  * Some characters for the LED control registers
@@ -51,24 +51,24 @@
  * control each of the seven segments and the dot independently.
  * It's only a toy, anyway...
  */
-#define LED_DOT                 0x01
-#define LED_SPACE               0x00
-#define LED_0                   0xfc
-#define LED_1                   0x60
-#define LED_2                   0xda
-#define LED_3                   0xf2
-#define LED_4                   0x66
-#define LED_5                   0xb6
-#define LED_6                   0xbe
-#define LED_7                   0xe0
-#define LED_8                   0xfe
-#define LED_9                   0xf6
-#define LED_A                   0xee
-#define LED_b                   0x3e
-#define LED_C                   0x9c
-#define LED_d                   0x7a
-#define LED_E                   0x9e
-#define LED_F                   0x8e
+#define LED_DOT			0x01
+#define LED_SPACE		0x00
+#define LED_0			0xfc
+#define LED_1			0x60
+#define LED_2			0xda
+#define LED_3			0xf2
+#define LED_4			0x66
+#define LED_5			0xb6
+#define LED_6			0xbe
+#define LED_7			0xe0
+#define LED_8			0xfe
+#define LED_9			0xf6
+#define LED_A			0xee
+#define LED_b			0x3e
+#define LED_C			0x9c
+#define LED_d			0x7a
+#define LED_E			0x9e
+#define LED_F			0x8e
 
 #ifndef __ASSEMBLY__
 
@@ -96,9 +96,9 @@ static __inline__ void pica_set_led(unsigned int bits)
  * This address is just a guess and seems to differ from
  * other mips machines such as RC3xxx...
  */
-#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
-#define JAZZ_KEYBOARD_DATA      0xe0005000
-#define JAZZ_KEYBOARD_COMMAND   0xe0005001
+#define JAZZ_KEYBOARD_ADDRESS	0xe0005000
+#define JAZZ_KEYBOARD_DATA	0xe0005000
+#define JAZZ_KEYBOARD_COMMAND	0xe0005001
 
 #ifndef __ASSEMBLY__
 
@@ -119,28 +119,28 @@ typedef struct {
 /*
  * For now. Needs to be changed for RC3xxx support. See below.
  */
-#define keyboard_hardware       jazz_keyboard_hardware
+#define keyboard_hardware	jazz_keyboard_hardware
 
 #endif /* !__ASSEMBLY__ */
 
 /*
  * i8042 keyboard controller for most other Mips machines.
  */
-#define MIPS_KEYBOARD_ADDRESS   0xb9005000
-#define MIPS_KEYBOARD_DATA      0xb9005003
-#define MIPS_KEYBOARD_COMMAND   0xb9005007
+#define MIPS_KEYBOARD_ADDRESS	0xb9005000
+#define MIPS_KEYBOARD_DATA	0xb9005003
+#define MIPS_KEYBOARD_COMMAND	0xb9005007
 
 /*
  * Serial and parallel ports (WD 16C552) on the Mips JAZZ
  */
-#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
-#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
-#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
+#define JAZZ_SERIAL1_BASE	(unsigned int)0xe0006000
+#define JAZZ_SERIAL2_BASE	(unsigned int)0xe0007000
+#define JAZZ_PARALLEL_BASE	(unsigned int)0xe0008000
 
 /*
  * Dummy Device Address. Used in jazzdma.c
  */
-#define JAZZ_DUMMY_DEVICE       0xe000d000
+#define JAZZ_DUMMY_DEVICE	0xe000d000
 
 /*
  * JAZZ timer registers and interrupt no.
@@ -148,8 +148,8 @@ typedef struct {
  * cpu level 6, but to keep compatibility with PC stuff
  * it is remapped to vector 0. See arch/mips/kernel/entry.S.
  */
-#define JAZZ_TIMER_INTERVAL     0xe0000228
-#define JAZZ_TIMER_REGISTER     0xe0000230
+#define JAZZ_TIMER_INTERVAL	0xe0000228
+#define JAZZ_TIMER_REGISTER	0xe0000230
 
 /*
  * DRAM configuration register
@@ -176,13 +176,13 @@ typedef struct {
 #endif
 #endif /* !__ASSEMBLY__ */
 
-#define PICA_DRAM_CONFIG        0xe00fffe0
+#define PICA_DRAM_CONFIG	0xe00fffe0
 
 /*
  * JAZZ interrupt control registers
  */
-#define JAZZ_IO_IRQ_SOURCE      0xe0010000
-#define JAZZ_IO_IRQ_ENABLE      0xe0010002
+#define JAZZ_IO_IRQ_SOURCE	0xe0010000
+#define JAZZ_IO_IRQ_ENABLE	0xe0010002
 
 /*
  * JAZZ Interrupt Level definitions
@@ -190,20 +190,20 @@ typedef struct {
  * This is somewhat broken.  For reasons which nobody can remember anymore
  * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
  */
-#define JAZZ_IRQ_START          24
-#define JAZZ_IRQ_END            (24 + 9)
-#define JAZZ_PARALLEL_IRQ       (JAZZ_IRQ_START + 0)
-#define JAZZ_FLOPPY_IRQ         (JAZZ_IRQ_START + 1)
-#define JAZZ_SOUND_IRQ          (JAZZ_IRQ_START + 2)
-#define JAZZ_VIDEO_IRQ          (JAZZ_IRQ_START + 3)
-#define JAZZ_ETHERNET_IRQ       (JAZZ_IRQ_START + 4)
-#define JAZZ_SCSI_IRQ           (JAZZ_IRQ_START + 5)
-#define JAZZ_KEYBOARD_IRQ       (JAZZ_IRQ_START + 6)
-#define JAZZ_MOUSE_IRQ          (JAZZ_IRQ_START + 7)
-#define JAZZ_SERIAL1_IRQ        (JAZZ_IRQ_START + 8)
-#define JAZZ_SERIAL2_IRQ        (JAZZ_IRQ_START + 9)
-
-#define JAZZ_TIMER_IRQ          (MIPS_CPU_IRQ_BASE+6)
+#define JAZZ_IRQ_START		24
+#define JAZZ_IRQ_END		(24 + 9)
+#define JAZZ_PARALLEL_IRQ	(JAZZ_IRQ_START + 0)
+#define JAZZ_FLOPPY_IRQ		(JAZZ_IRQ_START + 1)
+#define JAZZ_SOUND_IRQ		(JAZZ_IRQ_START + 2)
+#define JAZZ_VIDEO_IRQ		(JAZZ_IRQ_START + 3)
+#define JAZZ_ETHERNET_IRQ	(JAZZ_IRQ_START + 4)
+#define JAZZ_SCSI_IRQ		(JAZZ_IRQ_START + 5)
+#define JAZZ_KEYBOARD_IRQ	(JAZZ_IRQ_START + 6)
+#define JAZZ_MOUSE_IRQ		(JAZZ_IRQ_START + 7)
+#define JAZZ_SERIAL1_IRQ	(JAZZ_IRQ_START + 8)
+#define JAZZ_SERIAL2_IRQ	(JAZZ_IRQ_START + 9)
+
+#define JAZZ_TIMER_IRQ		(MIPS_CPU_IRQ_BASE+6)
 
 
 /*
@@ -211,46 +211,46 @@ typedef struct {
  * Note: Channels 4...7 are not used with respect to the Acer PICA-61
  * chipset which does not provide these DMA channels.
  */
-#define JAZZ_SCSI_DMA           0              /* SCSI */
-#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
-#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
-#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
+#define JAZZ_SCSI_DMA		0	       /* SCSI */
+#define JAZZ_FLOPPY_DMA		1	       /* FLOPPY */
+#define JAZZ_AUDIOL_DMA		2	       /* AUDIO L */
+#define JAZZ_AUDIOR_DMA		3	       /* AUDIO R */
 
 /*
  * JAZZ R4030 MCT_ADR chip (DMA controller)
  * Note: Virtual Addresses !
  */
 #define JAZZ_R4030_CONFIG	0xE0000000	/* R4030 config register */
-#define JAZZ_R4030_REVISION     0xE0000008	/* same as PICA_ASIC_REVISION */
+#define JAZZ_R4030_REVISION	0xE0000008	/* same as PICA_ASIC_REVISION */
 #define JAZZ_R4030_INV_ADDR	0xE0000010	/* Invalid Address register */
 
-#define JAZZ_R4030_TRSTBL_BASE  0xE0000018	/* Translation Table Base */
-#define JAZZ_R4030_TRSTBL_LIM   0xE0000020	/* Translation Table Limit */
-#define JAZZ_R4030_TRSTBL_INV   0xE0000028	/* Translation Table Invalidate */
+#define JAZZ_R4030_TRSTBL_BASE	0xE0000018	/* Translation Table Base */
+#define JAZZ_R4030_TRSTBL_LIM	0xE0000020	/* Translation Table Limit */
+#define JAZZ_R4030_TRSTBL_INV	0xE0000028	/* Translation Table Invalidate */
 
-#define JAZZ_R4030_CACHE_MTNC   0xE0000030	/* Cache Maintenance */
-#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038	/* Remote Failed Address */
-#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040	/* Memory Failed Address */
+#define JAZZ_R4030_CACHE_MTNC	0xE0000030	/* Cache Maintenance */
+#define JAZZ_R4030_R_FAIL_ADDR	0xE0000038	/* Remote Failed Address */
+#define JAZZ_R4030_M_FAIL_ADDR	0xE0000040	/* Memory Failed Address */
 
-#define JAZZ_R4030_CACHE_PTAG   0xE0000048	/* I/O Cache Physical Tag */
-#define JAZZ_R4030_CACHE_LTAG   0xE0000050	/* I/O Cache Logical Tag */
-#define JAZZ_R4030_CACHE_BMASK  0xE0000058	/* I/O Cache Byte Mask */
-#define JAZZ_R4030_CACHE_BWIN   0xE0000060	/* I/O Cache Buffer Window */
+#define JAZZ_R4030_CACHE_PTAG	0xE0000048	/* I/O Cache Physical Tag */
+#define JAZZ_R4030_CACHE_LTAG	0xE0000050	/* I/O Cache Logical Tag */
+#define JAZZ_R4030_CACHE_BMASK	0xE0000058	/* I/O Cache Byte Mask */
+#define JAZZ_R4030_CACHE_BWIN	0xE0000060	/* I/O Cache Buffer Window */
 
 /*
  * Remote Speed Registers.
  *
- *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
- *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
- *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
+ *  0: free,	  1: Ethernet,	2: SCSI,      3: Floppy,
+ *  4: RTC,	  5: Kb./Mouse	6: serial 1,  7: serial 2,
+ *  8: parallel,  9: NVRAM,    10: CPU,	     11: PROM,
  * 12: reserved, 13: free,     14: 7seg LED, 15: ???
  */
 #define JAZZ_R4030_REM_SPEED	0xE0000070	/* 16 Remote Speed Registers */
 						/* 0xE0000070,78,80... 0xE00000E8 */
-#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8	/* Internal Interrupt Enable */
-#define JAZZ_R4030_INVAL_ADDR   0xE0000010	/* Invalid address Register */
-#define JAZZ_R4030_IRQ_SOURCE   0xE0000200	/* Interrupt Source Register */
-#define JAZZ_R4030_I386_ERROR   0xE0000208	/* i386/EISA Bus Error */
+#define JAZZ_R4030_IRQ_ENABLE	0xE00000E8	/* Internal Interrupt Enable */
+#define JAZZ_R4030_INVAL_ADDR	0xE0000010	/* Invalid address Register */
+#define JAZZ_R4030_IRQ_SOURCE	0xE0000200	/* Interrupt Source Register */
+#define JAZZ_R4030_I386_ERROR	0xE0000208	/* i386/EISA Bus Error */
 
 /*
  * Virtual (E)ISA controller address