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| author | Petar Jovanovic <petar.jovanovic@rt-rk.com> | 2017-03-15 18:59:11 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-29 15:21:52 +0200 |
| commit | 846fbcfe6ffdcc86720df347e919f0389a69e6a0 (patch) | |
| tree | 1241b5943a634ee0799579797588233f07714fa1 /arch/mips/include/asm/mach-cavium-octeon | |
| parent | MIPS: signal: Remove unreachable code from force_fcr31_sig(). (diff) | |
| download | linux-846fbcfe6ffdcc86720df347e919f0389a69e6a0.tar.xz linux-846fbcfe6ffdcc86720df347e919f0389a69e6a0.zip | |
MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1
Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.
Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: petar.jovanovic@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15749/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon')
| -rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index bd8b9bbe1771..a4f798629c3d 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -46,9 +46,9 @@ #define cpu_has_64bits 1 #define cpu_has_octeon_cache 1 #define cpu_has_saa octeon_has_saa() -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 1 #define cpu_has_mips64r2 1 #define cpu_has_dsp 0 #define cpu_has_dsp2 0 |