diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2010-06-01 22:18:15 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-08-05 14:26:20 +0200 |
| commit | ca148125e6134de334b61822539d220794d8da18 (patch) | |
| tree | e31af5840a8873ec6613bf9b09fe0f9ad3e6a9c7 /arch/mips/include/asm/mach-cavium-octeon | |
| parent | MIPS: JZ4740: Add qi_lb60 board support (diff) | |
| download | linux-ca148125e6134de334b61822539d220794d8da18.tar.xz linux-ca148125e6134de334b61822539d220794d8da18.zip | |
MIPS: Octeon: Implement delays with cycle counter.
Power throttling make deterministic delay loops impossible.
Re-implement delays using the cycle counter. This also allows us to
get rid of the code that calculates loops per jiffy.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1317/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon')
| -rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 2a7ea90fee2a..b952fc7215e2 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -61,22 +61,11 @@ #define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) -#define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 #define spin_lock_prefetch(x) prefetch(x) #define PREFETCH_STRIDE 128 -static inline int read_current_timer(unsigned long *result) -{ - asm volatile ("rdhwr %0,$31\n" -#ifndef CONFIG_64BIT - "\tsll %0, 0" -#endif - : "=r" (*result)); - return 0; -} - #ifdef __OCTEON__ /* * All gcc versions that have OCTEON support define __OCTEON__ and have the |