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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-08-24 18:32:47 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-09-07 22:24:09 +0200
commit24a1c023f3ff3082fee9c019c17e6a34e2ddfe6b (patch)
tree25ceb96a0bfd469da846b4140806161fe09fc806 /arch/mips/include/asm/mach-ip22
parentMIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR (diff)
downloadlinux-24a1c023f3ff3082fee9c019c17e6a34e2ddfe6b.tar.xz
linux-24a1c023f3ff3082fee9c019c17e6a34e2ddfe6b.zip
MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ip22')
-rw-r--r--arch/mips/include/asm/mach-ip22/war.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index e47a7e186ed2..35286ba3ec57 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0