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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:45 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:23:48 +0200 |
| commit | 44def3426e4ac5a2dbdb5c8304397f4daa38eb2f (patch) | |
| tree | 365e80bb0639308afa9500270f69b83fdd6f0d3b /arch/mips/include/asm/mach-ip22 | |
| parent | MIPS: Convert R4600_V1_HIT_CACHEOP into a config option (diff) | |
| download | linux-44def3426e4ac5a2dbdb5c8304397f4daa38eb2f.tar.xz linux-44def3426e4ac5a2dbdb5c8304397f4daa38eb2f.zip | |
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ip22')
| -rw-r--r-- | arch/mips/include/asm/mach-ip22/war.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h index 9154c54d428a..a5a1c41df74e 100644 --- a/arch/mips/include/asm/mach-ip22/war.h +++ b/arch/mips/include/asm/mach-ip22/war.h @@ -8,11 +8,6 @@ #ifndef __ASM_MIPS_MACH_IP22_WAR_H #define __ASM_MIPS_MACH_IP22_WAR_H -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ - -#define R4600_V2_HIT_CACHEOP_WAR 1 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 |