diff options
| author | Thomas Langer <thomas.langer@lantiq.com> | 2012-05-02 12:27:38 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-05-15 17:49:22 +0200 |
| commit | 7705f6867bfc6f2ea42c3965a85df72abf070c86 (patch) | |
| tree | 556ac1fafeb72b372873c404ab7e4cf47a917e63 /arch/mips/include/asm/mach-lantiq | |
| parent | MIPS: lantiq: add ipi handlers to make vsmp work (diff) | |
| download | linux-7705f6867bfc6f2ea42c3965a85df72abf070c86.tar.xz linux-7705f6867bfc6f2ea42c3965a85df72abf070c86.zip | |
MIPS: lantiq: fix early printk
The code was using a 32bit write operations in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. This patch
changes the memory access to 8bit.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3721/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-lantiq')
| -rw-r--r-- | arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 8a3c6be669d2..8bc9030525c0 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -34,6 +34,12 @@ #define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_ASC_SIZE 0x400 +/* + * during early_printk no ioremap is possible + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) + /* RCU - reset control unit */ #define LTQ_RCU_BASE_ADDR 0x1F203000 #define LTQ_RCU_SIZE 0x1000 |