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authorJayachandran C <jchandra@broadcom.com>2013-12-21 12:22:13 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-01-24 22:39:46 +0100
commitc24a8a7a99885d5b986f38f6631f69e7794a3e5e (patch)
treea0d6702fc1c45cba157a5734215c509fa4b216c6 /arch/mips/include/asm/mach-netlogic
parentMIPS: malta: Incorporate PIIX4 ACPI I/O region in PCI controller resources (diff)
downloadlinux-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.tar.xz
linux-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.zip
MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
Diffstat (limited to 'arch/mips/include/asm/mach-netlogic')
-rw-r--r--arch/mips/include/asm/mach-netlogic/irq.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index 868ed8a2ed5c..c0dbd530cca6 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -9,7 +9,8 @@
#define __ASM_NETLOGIC_IRQ_H
#include <asm/mach-netlogic/multi-node.h>
-#define NR_IRQS (64 * NLM_NR_NODES)
+#define NLM_IRQS_PER_NODE 1024
+#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
#define MIPS_CPU_IRQ_BASE 0