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| author | Ralf Baechle <ralf@linux-mips.org> | 2014-03-30 13:20:10 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 18:17:12 +0200 |
| commit | a809d46066d5171ed446d59a51cd1e57d99fcfc3 (patch) | |
| tree | ede5e0f23d1577da4685034894f66f1de2529937 /arch/mips/include/asm/mach-pmcs-msp71xx | |
| parent | MIPS: Fix core number detection for MT cores (diff) | |
| download | linux-a809d46066d5171ed446d59a51cd1e57d99fcfc3.tar.xz linux-a809d46066d5171ed446d59a51cd1e57d99fcfc3.zip | |
MIPS: Fix gigaton of warning building with microMIPS.
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III
mode through .set mips3 results in *lots* of warnings like
{standard input}: Assembler messages:
{standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
during a kernel build. Fixed by using .set arch=r4000 instead.
This breaks support for building the kernel with binutils 2.13 which
was supported for 32 bit kernels only anyway and 2.14 which was a bad
vintage for MIPS anyway.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-pmcs-msp71xx')
| -rw-r--r-- | arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h index 2dbc7a8cec1a..fc946c835995 100644 --- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h @@ -76,7 +76,7 @@ static inline void set_value_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # set_value_reg32 \n" " and %0, %2 \n" " or %0, %3 \n" @@ -98,7 +98,7 @@ static inline void set_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # set_reg32 \n" " or %0, %2 \n" " sc %0, %1 \n" @@ -119,7 +119,7 @@ static inline void clear_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # clear_reg32 \n" " and %0, %2 \n" " sc %0, %1 \n" @@ -140,7 +140,7 @@ static inline void toggle_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # toggle_reg32 \n" " xor %0, %2 \n" " sc %0, %1 \n" @@ -216,7 +216,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr) #define custom_read_reg32(address, tmp) \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ "1: ll %0, %1 #custom_read_reg32 \n" \ " .set pop \n" \ : "=r" (tmp), "=m" (*address) \ @@ -225,7 +225,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr) #define custom_write_reg32(address, tmp) \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ " sc %0, %1 #custom_write_reg32 \n" \ " "__beqz"%0, 1b \n" \ " nop \n" \ |