Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:

 o Add basic support for the Mediatek/Ralink Wireless SoC family.

 o The Qualcomm Atheros platform is extended by support for the new
   QCA955X SoC series as well as a bunch of patches that get the code
   ready for OF support.

 o Lantiq and BCM47XX platform have a few improvements and bug fixes.

 o MIPS has sent a few patches that get the kernel ready for the
   upcoming microMIPS support.

 o The rest of the series is made up of small bug fixes and cleanups
   that relate to various parts of the MIPS code.  The biggy in there is
   a whitespace cleanup.  After I was sent another set of whitespace
   cleanup patches I decided it was the time to clean the whitespace
   "issues" for once and and that touches many files below arch/mips/.

Fix up silly conflicts, mostly due to whitespace cleanups.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
  MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
  MIPS: remove broken conditional inside vpe loader code
  MIPS: SMTC: fix implicit declaration of set_vi_handler
  MIPS: early_printk: drop __init annotations
  MIPS: Probe for and report hardware virtualization support.
  MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
  MIPS: ath79: add USB controller registration code for the QCA955X SoCs
  MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
  MIPS: ath79: add WMAC registration code for the QCA955X SoCs
  MIPS: ath79: register UART for the QCA955X SoCs
  MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
  MIPS: ath79: add GPIO setup code for the QCA955X SoCs
  MIPS: ath79: add IRQ handling code for the QCA955X SoCs
  MIPS: ath79: add clock setup code for the QCA955X SoCs
  MIPS: ath79: add SoC detection code for the QCA955X SoCs
  MIPS: ath79: add early printk support for the QCA955X SoCs
  MIPS: ath79: fix WMAC IRQ resource assignment
  mips: reserve elfcorehdr
  mips: Make sure kernel memory is in iomem
  MIPS: ath79: use dynamically allocated USB platform devices
  ...

1 files changed, 8 insertions, 8 deletions

diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
index 83746b84a5ec..00fa3684ac98 100644
--- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
@@ -1,6 +1,6 @@
 /*
  * This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
+ * search and replace.	The numbers are the same.
  *
  * The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.
@@ -11,11 +11,11 @@
 /*
  * This is the CPU physical memory map of PPMC Board:
  *
- *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
- *    0x1C000000-0x1C000000      - LED (CS0)
- *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
- *    0x1F000000-0x1F000000      - MailBox (CS3)
- *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
+ *    0x00000000-0x03FFFFFF	 - 64MB SDRAM (SCS[0]#)
+ *    0x1C000000-0x1C000000	 - LED (CS0)
+ *    0x1C800000-0x1C800007	 - UART 16550 port (CS1)
+ *    0x1F000000-0x1F000000	 - MailBox (CS3)
+ *    0x1FC00000-0x20000000	 - 4MB Flash (BOOT CS)
  */
 
 #define WRPPMC_SDRAM_SCS0_BASE	0x00000000
@@ -39,8 +39,8 @@
  *
  * NOTE: We only have PCI_0 hose interface
  */
-#define GT_PCI_MEM_BASE	0x13000000UL
-#define GT_PCI_MEM_SIZE	0x02000000UL
+#define GT_PCI_MEM_BASE 0x13000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
 #define GT_PCI_IO_BASE	0x11000000UL
 #define GT_PCI_IO_SIZE	0x02000000UL