diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-07-09 11:40:47 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-08-26 15:23:15 +0200 |
| commit | 3885c2b463f6a236e47df22ef13d13433006b951 (patch) | |
| tree | 1b78aa7bfd080ea95caae4935f869e1bad7396f8 /arch/mips/include/asm/mips-cm.h | |
| parent | MIPS: CPC: Fix type for GCR CPC base reg for 64-bit (diff) | |
| download | linux-3885c2b463f6a236e47df22ef13d13433006b951.tar.xz linux-3885c2b463f6a236e47df22ef13d13433006b951.zip | |
MIPS: CM: Add support for reporting CM cache errors
The CM cache error reporting code is not Malta specific and as such it
should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the
way cache errors are being recorded to the registers so extend the
previous code to add support for the CM3 as well.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10646/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mips-cm.h')
| -rw-r--r-- | arch/mips/include/asm/mips-cm.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 46cc0c69b77c..d75b75e78ebb 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -48,6 +48,15 @@ extern phys_addr_t __mips_cm_phys_base(void); extern int mips_cm_is64; /** + * mips_cm_error_report - Report CM cache errors + */ +#ifdef CONFIG_MIPS_CM +extern void mips_cm_error_report(void); +#else +static inline void mips_cm_error_report(void) {} +#endif + +/** * mips_cm_probe - probe for a Coherence Manager * * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM |