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| author | James Hogan <james.hogan@imgtec.com> | 2016-06-15 20:29:59 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2016-06-15 23:58:38 +0200 |
| commit | 4b34bca0e4c7091a06d774342faf8c9a4836af22 (patch) | |
| tree | 8cd4c322296ff4d2c97ce2ac83fa01afefccbc6d /arch/mips/include/asm/mipsregs.h | |
| parent | MIPS: KVM: Use host CCA for TLB mappings (diff) | |
| download | linux-4b34bca0e4c7091a06d774342faf8c9a4836af22.tar.xz linux-4b34bca0e4c7091a06d774342faf8c9a4836af22.zip | |
MIPS: Add define for Config.VI (virtual icache) bit
The Config.VI bit specifies that the instruction cache is virtually
tagged, which is checked in c-r4k.c's probe_pcache(). Add a proper
definition for it in mipsregs.h and make use of it.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 8b1b37d50d15..def9d8d13f6e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -533,6 +533,7 @@ #define TX49_CONF_CWFON (_ULCAST_(1) << 27) /* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_VI (_ULCAST_(1) << 3) #define MIPS_CONF_MT (_ULCAST_(7) << 7) #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) |