diff options
| author | James Hogan <james.hogan@imgtec.com> | 2016-05-11 14:50:49 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:30:25 +0200 |
| commit | 37af2f3077d9202f8f8d17f453c91c9d08e11c76 (patch) | |
| tree | e9a4bed870e5ce0ffc8fd213144dde8b4755c92e /arch/mips/include/asm/mipsregs.h | |
| parent | MIPS: alchemy: Remove CLK_IS_ROOT (diff) | |
| download | linux-37af2f3077d9202f8f8d17f453c91c9d08e11c76.tar.xz linux-37af2f3077d9202f8f8d17f453c91c9d08e11c76.zip | |
MIPS: Define & use CP0_EBase bit definitions
Add definitions for the bits & fields in the CP0_EBase register, and use
them from a few different places in arch/mips which hardcoded these
values.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13222/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index b7705ef09df2..57d72f2bf745 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -676,6 +676,14 @@ #define MIPS_MAAR_S (_ULCAST_(1) << 1) #define MIPS_MAAR_V (_ULCAST_(1) << 0) +/* EBase bit definitions */ +#define MIPS_EBASE_CPUNUM_SHIFT 0 +#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0) +#define MIPS_EBASE_WG_SHIFT 11 +#define MIPS_EBASE_WG (_ULCAST_(1) << 11) +#define MIPS_EBASE_BASE_SHIFT 12 +#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1)) + /* CMGCRBase bit definitions */ #define MIPS_CMGCRB_BASE 11 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) @@ -2104,7 +2112,7 @@ __BUILD_SET_C0(brcm_mode) */ static inline unsigned int get_ebase_cpunum(void) { - return read_c0_ebase() & 0x3ff; + return read_c0_ebase() & MIPS_EBASE_CPUNUM; } #endif /* !__ASSEMBLY__ */ |