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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-02-19 16:57:20 +0100
committerPaul Burton <paul.burton@mips.com>2019-02-19 21:46:03 +0100
commit69a07a41d908f9df48393bbab179daded8cfab66 (patch)
tree6764897f28cee05ecd539010ce61c4138b3bfdc5 /arch/mips/include/asm/pci
parentMIPS: SGI-IP27: do boot CPU init later (diff)
downloadlinux-69a07a41d908f9df48393bbab179daded8cfab66.tar.xz
linux-69a07a41d908f9df48393bbab179daded8cfab66.zip
MIPS: SGI-IP27: rework HUB interrupts
This commit rearranges the HUB interrupt code by using MIPS_IRQ_CPU interrupt handling code and modern Linux IRQ framework features to get rid of global arrays. It also adds support for irq affinity setting. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm/pci')
-rw-r--r--arch/mips/include/asm/pci/bridge.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index 0c5fe3a2d2a9..23574c27eb40 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -808,7 +808,6 @@ struct bridge_controller {
struct bridge_regs *base;
nasid_t nasid;
unsigned int widget_id;
- unsigned int irq_cpu;
u64 baddr;
unsigned int pci_int[8];
};
@@ -823,8 +822,7 @@ struct bridge_controller {
#define bridge_clr(bc, reg, val) \
__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
-extern void register_bridge_irq(unsigned int irq);
-extern int request_bridge_irq(struct bridge_controller *bc);
+extern int request_bridge_irq(struct bridge_controller *bc, int pin);
extern struct pci_ops bridge_pci_ops;