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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-06-09 07:34:53 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-06-09 07:34:53 +0200
commit38a4671cad3f0d277cf48445b49e42a475ebfb6a (patch)
tree7348f3dd5f4e1bec39758dcff748a9dcbbf3430c /arch/mips/include/asm/ptrace.h
parentpcmcia/trivial: at91_cf: fix checkpatch error (diff)
parentLinux 3.10-rc5 (diff)
downloadlinux-38a4671cad3f0d277cf48445b49e42a475ebfb6a.tar.xz
linux-38a4671cad3f0d277cf48445b49e42a475ebfb6a.zip
Merge 3.10-rc5 into char-misc-next
Diffstat (limited to 'arch/mips/include/asm/ptrace.h')
-rw-r--r--arch/mips/include/asm/ptrace.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index a3186f2bb8a0..5e6cd0947393 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -16,6 +16,38 @@
#include <asm/isadep.h>
#include <uapi/asm/ptrace.h>
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+ /* Pad bytes for argument save space on the stack. */
+ unsigned long pad0[6];
+#endif
+
+ /* Saved main processor registers. */
+ unsigned long regs[32];
+
+ /* Saved special registers. */
+ unsigned long cp0_status;
+ unsigned long hi;
+ unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+ unsigned long acx;
+#endif
+ unsigned long cp0_badvaddr;
+ unsigned long cp0_cause;
+ unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+ unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[3]; /* MTM{0,1,2} */
+ unsigned long long mtp[3]; /* MTP{0,1,2} */
+#endif
+} __aligned(8);
+
struct task_struct;
extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);