MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 52 insertions, 52 deletions

diff --git a/arch/mips/include/asm/sni.h b/arch/mips/include/asm/sni.h
index 8c1eb02c6d16..a107201a2e1e 100644
--- a/arch/mips/include/asm/sni.h
+++ b/arch/mips/include/asm/sni.h
@@ -13,27 +13,27 @@
 
 extern unsigned int sni_brd_type;
 
-#define SNI_BRD_10                 2
-#define SNI_BRD_10NEW              3
-#define SNI_BRD_TOWER_OASIC        4
-#define SNI_BRD_MINITOWER          5
-#define SNI_BRD_PCI_TOWER          6
-#define SNI_BRD_RM200              7
-#define SNI_BRD_PCI_MTOWER         8
-#define SNI_BRD_PCI_DESKTOP        9
-#define SNI_BRD_PCI_TOWER_CPLUS   10
+#define SNI_BRD_10		   2
+#define SNI_BRD_10NEW		   3
+#define SNI_BRD_TOWER_OASIC	   4
+#define SNI_BRD_MINITOWER	   5
+#define SNI_BRD_PCI_TOWER	   6
+#define SNI_BRD_RM200		   7
+#define SNI_BRD_PCI_MTOWER	   8
+#define SNI_BRD_PCI_DESKTOP	   9
+#define SNI_BRD_PCI_TOWER_CPLUS	  10
 #define SNI_BRD_PCI_MTOWER_CPLUS  11
 
 /* RM400 cpu types */
-#define SNI_CPU_M8021           0x01
-#define SNI_CPU_M8030           0x04
-#define SNI_CPU_M8031           0x06
-#define SNI_CPU_M8034           0x0f
-#define SNI_CPU_M8037           0x07
-#define SNI_CPU_M8040           0x05
-#define SNI_CPU_M8043           0x09
-#define SNI_CPU_M8050           0x0b
-#define SNI_CPU_M8053           0x0d
+#define SNI_CPU_M8021		0x01
+#define SNI_CPU_M8030		0x04
+#define SNI_CPU_M8031		0x06
+#define SNI_CPU_M8034		0x0f
+#define SNI_CPU_M8037		0x07
+#define SNI_CPU_M8040		0x05
+#define SNI_CPU_M8043		0x09
+#define SNI_CPU_M8050		0x0b
+#define SNI_CPU_M8053		0x0d
 
 #define SNI_PORT_BASE		CKSEG1ADDR(0xb4000000)
 
@@ -52,14 +52,14 @@ extern unsigned int sni_brd_type;
 #define PCIMT_ERRADDR		CKSEG1ADDR(0xbfff0044)
 #define PCIMT_SYNDROME		CKSEG1ADDR(0xbfff004c)
 #define PCIMT_ITPEND		CKSEG1ADDR(0xbfff0054)
-#define  IT_INT2		0x01
-#define  IT_INTD		0x02
-#define  IT_INTC		0x04
-#define  IT_INTB		0x08
-#define  IT_INTA		0x10
-#define  IT_EISA		0x20
-#define  IT_SCSI		0x40
-#define  IT_ETH			0x80
+#define	 IT_INT2		0x01
+#define	 IT_INTD		0x02
+#define	 IT_INTC		0x04
+#define	 IT_INTB		0x08
+#define	 IT_INTA		0x10
+#define	 IT_EISA		0x20
+#define	 IT_SCSI		0x40
+#define	 IT_ETH			0x80
 #define PCIMT_IRQSEL		CKSEG1ADDR(0xbfff005c)
 #define PCIMT_TESTMEM		CKSEG1ADDR(0xbfff0064)
 #define PCIMT_ECCREG		CKSEG1ADDR(0xbfff006c)
@@ -86,14 +86,14 @@ extern unsigned int sni_brd_type;
 #define PCIMT_ERRADDR		CKSEG1ADDR(0xbfff0040)
 #define PCIMT_SYNDROME		CKSEG1ADDR(0xbfff0048)
 #define PCIMT_ITPEND		CKSEG1ADDR(0xbfff0050)
-#define  IT_INT2		0x01
-#define  IT_INTD		0x02
-#define  IT_INTC		0x04
-#define  IT_INTB		0x08
-#define  IT_INTA		0x10
-#define  IT_EISA		0x20
-#define  IT_SCSI		0x40
-#define  IT_ETH			0x80
+#define	 IT_INT2		0x01
+#define	 IT_INTD		0x02
+#define	 IT_INTC		0x04
+#define	 IT_INTB		0x08
+#define	 IT_INTA		0x10
+#define	 IT_EISA		0x20
+#define	 IT_SCSI		0x40
+#define	 IT_ETH			0x80
 #define PCIMT_IRQSEL		CKSEG1ADDR(0xbfff0058)
 #define PCIMT_TESTMEM		CKSEG1ADDR(0xbfff0060)
 #define PCIMT_ECCREG		CKSEG1ADDR(0xbfff0068)
@@ -137,29 +137,29 @@ extern unsigned int sni_brd_type;
 /*
  * A20R based boards
  */
-#define A20R_PT_CLOCK_BASE      CKSEG1ADDR(0xbc040000)
-#define A20R_PT_TIM0_ACK        CKSEG1ADDR(0xbc050000)
-#define A20R_PT_TIM1_ACK        CKSEG1ADDR(0xbc060000)
+#define A20R_PT_CLOCK_BASE	CKSEG1ADDR(0xbc040000)
+#define A20R_PT_TIM0_ACK	CKSEG1ADDR(0xbc050000)
+#define A20R_PT_TIM1_ACK	CKSEG1ADDR(0xbc060000)
 
-#define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
-#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
+#define SNI_A20R_IRQ_BASE	MIPS_CPU_IRQ_BASE
+#define SNI_A20R_IRQ_TIMER	(SNI_A20R_IRQ_BASE+5)
 
-#define SNI_PCIT_INT_REG        CKSEG1ADDR(0xbfff000c)
+#define SNI_PCIT_INT_REG	CKSEG1ADDR(0xbfff000c)
 
-#define SNI_PCIT_INT_START      24
-#define SNI_PCIT_INT_END        30
+#define SNI_PCIT_INT_START	24
+#define SNI_PCIT_INT_END	30
 
-#define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)
-#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
-#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
-#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
-#define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
-#define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
-#define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
+#define PCIT_IRQ_ETHERNET	(MIPS_CPU_IRQ_BASE + 5)
+#define PCIT_IRQ_INTA		(SNI_PCIT_INT_START + 0)
+#define PCIT_IRQ_INTB		(SNI_PCIT_INT_START + 1)
+#define PCIT_IRQ_INTC		(SNI_PCIT_INT_START + 2)
+#define PCIT_IRQ_INTD		(SNI_PCIT_INT_START + 3)
+#define PCIT_IRQ_SCSI0		(SNI_PCIT_INT_START + 4)
+#define PCIT_IRQ_SCSI1		(SNI_PCIT_INT_START + 5)
 
 
 /*
- * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
+ * Interrupt 0-16 are EISA interrupts.	Interrupts from 16 on are assigned
  * to the other interrupts generated by ASIC PCI.
  *
  * INT2 is a wired-or of the push button interrupt, high temperature interrupt
@@ -204,12 +204,12 @@ extern unsigned int sni_brd_type;
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define __SNI_END 3
 #endif
-#define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
+#define SNI_IDPROM_BASE	       CKSEG1ADDR(0x1ff00000)
 #define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
 #define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
 #define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
 
-#define SNI_IDPROM_SIZE	0x1000
+#define SNI_IDPROM_SIZE 0x1000
 
 /* board specific init functions */
 extern void sni_a20r_init(void);