diff options
| author | Huacai Chen <chenhc@lemote.com> | 2014-06-26 05:41:28 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-07-30 21:46:19 +0200 |
| commit | c46173183657bbdbe0d54a981c28807581648422 (patch) | |
| tree | 554d75cfc577d82c043b3e2fca17819abd63033b /arch/mips/include/asm/sparsemem.h | |
| parent | MIPS: Loongson: Modify ChipConfig register definition (diff) | |
| download | linux-c46173183657bbdbe0d54a981c28807581648422.tar.xz linux-c46173183657bbdbe0d54a981c28807581648422.zip | |
MIPS: Add NUMA support for Loongson-3
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is
a CC-NUMA system that every chip (node) has its own local memory and
cache coherency is maintained by hardware. The 64-bit physical memory
address format is as follows:
0x-0000-YZZZ-ZZZZ-ZZZZ
The high 16 bits should be 0, which means the real physical address
supported by Loongson-3 is 48-bit. The "Y" bits is the base address of
each node, which can be also considered as the node-id. The "Z" bits is
the address offset within a node, which means every node has a 44 bits
address space.
Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally,
because many other MIPS CPUs have also extended their address spaces.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7187/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/sparsemem.h')
| -rw-r--r-- | arch/mips/include/asm/sparsemem.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h index d2da53c2c2f8..b1071c1e54f5 100644 --- a/arch/mips/include/asm/sparsemem.h +++ b/arch/mips/include/asm/sparsemem.h @@ -11,7 +11,7 @@ #else # define SECTION_SIZE_BITS 28 #endif -#define MAX_PHYSMEM_BITS 35 +#define MAX_PHYSMEM_BITS 48 #endif /* CONFIG_SPARSEMEM */ #endif /* _MIPS_SPARSEMEM_H */ |