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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:44 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:23:38 +0200 |
| commit | 5e5b6527128cea50f12a7064bf61b130b3a2739a (patch) | |
| tree | 6dcaaf2a258785705bacc2447f4f639f575aa4c6 /arch/mips/include/asm/war.h | |
| parent | MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option (diff) | |
| download | linux-5e5b6527128cea50f12a7064bf61b130b3a2739a.tar.xz linux-5e5b6527128cea50f12a7064bf61b130b3a2739a.zip | |
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/war.h')
| -rw-r--r-- | arch/mips/include/asm/war.h | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 3c8923692fca..d336a0e57093 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -73,37 +73,6 @@ #endif /* - * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: - * - * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, - * Hit_Invalidate_D and Create_Dirty_Excl_D should only be - * executed if there is no other dcache activity. If the dcache is - * accessed for another instruction immeidately preceding when these - * cache instructions are executing, it is possible that the dcache - * tag match outputs used by these cache instructions will be - * incorrect. These cache instructions should be preceded by at least - * four instructions that are not any kind of load or store - * instruction. - * - * This is not allowed: lw - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * This is allowed: lw - * nop - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - */ -#ifndef R4600_V1_HIT_CACHEOP_WAR -#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform -#endif - - -/* * Writeback and invalidate the primary cache dcache before DMA. * * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, |