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| author | Manuel Lauss <mano@roarinelk.homelinux.net> | 2009-03-25 17:49:30 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-03-30 14:49:46 +0200 |
| commit | 2f794d099da2f081de2fe19b289a3aa807f735fa (patch) | |
| tree | 9d4065219b135c17c94a532fd8b4d51e49535f72 /arch/mips/include/asm | |
| parent | MIPS: Alchemy: provide cpu feature overrides. (diff) | |
| download | linux-2f794d099da2f081de2fe19b289a3aa807f735fa.tar.xz linux-2f794d099da2f081de2fe19b289a3aa807f735fa.zip | |
MIPS: Alchemy: MIPS hazard workarounds are not required.
The Alchemy manuals state:
"All pipeline hazards and dependencies are enforced by hardware interlocks
so that any sequence of instructions is guaranteed to execute correctly.
Therefore, it is not necessary to pad legacy MIPS hazards (such as
load delay slots and coprocessor accesses) with NOPs."
Run-tested on Au12x0, without any ill effects.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 134e1fc8f4d6..a12d971db4f9 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -87,7 +87,7 @@ do { \ : "=r" (tmp)); \ } while (0) -#elif defined(CONFIG_CPU_MIPSR1) +#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY) /* * These are slightly complicated by the fact that we guarantee R1 kernels to @@ -139,7 +139,7 @@ do { \ } while (0) #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_R5500) + defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |