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authorRalf Baechle <ralf@linux-mips.org>2012-11-30 17:27:27 +0100
committerRalf Baechle <ralf@linux-mips.org>2012-12-13 18:15:24 +0100
commitf772cdb2bd544eeb3e83a8bb42629d155c1b53fd (patch)
treebb368b90fd756fa08476fecb1efa3dea2f09f41f /arch/mips/include
parentMIPS: Remove usage of CSRC_R4K_LIB config option. (diff)
downloadlinux-f772cdb2bd544eeb3e83a8bb42629d155c1b53fd.tar.xz
linux-f772cdb2bd544eeb3e83a8bb42629d155c1b53fd.zip
MIPS: Remove usage of CEVT_R4K_LIB config option.
Manuel Lauss <manuel.lauss@gmail.com> writes: I introduced it as a fallback because early revisions of Alchemy hardware we shipped had a non-functional 32kHz timer and had to rely on the r4k timer instead. Previously the r4k timer was initialized regardless, but it's useless with the "wait" instruction. So long story short: I need either the on-chip 32kHz timer OR the r4k timer if the 32kHz one is unusable, but not both, and r4k timer is useless when au1k_idle is in use. The current in-kernel Alchemy boards all work with the 32kHz timer, so I'm not against removing R4K_LIB symbols. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/time.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 6be93a468ec9..761f2e92119e 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,10 +50,8 @@ extern int (*perf_irq)(void);
/*
* Initialize the calling CPU's compare interrupt as clockevent device
*/
-#ifdef CONFIG_CEVT_R4K_LIB
extern unsigned int __weak get_c0_compare_int(void);
extern int r4k_clockevent_init(void);
-#endif
static inline int mips_clockevent_init(void)
{