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| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-07-18 11:51:32 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-09-22 13:35:53 +0200 |
| commit | 4f12b91d2da577d81c580da62373fd37b31e0da1 (patch) | |
| tree | cb479c8808fdb05a00fa7d816fea0e5af4cbcfbb /arch/mips/include | |
| parent | MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores (diff) | |
| download | linux-4f12b91d2da577d81c580da62373fd37b31e0da1.tar.xz linux-4f12b91d2da577d81c580da62373fd37b31e0da1.zip | |
MIPS: cpu-probe: Set the write-combine CCA value on per core basis
Different cores use different CCA values to achieve write-combine
memory writes. For cores that do not support write-combine we
set the default value to CCA:2 (uncached, non-coherent) which is the
default value as set by the kernel.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7402/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cpu-info.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index d5f42c168001..a6c9ccb33c5c 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -79,6 +79,11 @@ struct cpuinfo_mips { #define NUM_WATCH_REGS 4 u16 watch_reg_masks[NUM_WATCH_REGS]; unsigned int kscratch_mask; /* Usable KScratch mask. */ + /* + * Cache Coherency attribute for write-combine memory writes. + * (shifted by _CACHE_SHIFT) + */ + unsigned int writecombine; } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; |