diff options
| author | James Hogan <james.hogan@imgtec.com> | 2015-07-15 17:17:44 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-09-03 12:07:47 +0200 |
| commit | aaa7be48fdbf14836ff1bc61c72969960a5923c6 (patch) | |
| tree | 59499e1cba6e4d350949b3a4a90695ba47b0a9eb /arch/mips/include | |
| parent | MIPS: Refactor dumping of TLB registers for r3k/r4k (diff) | |
| download | linux-aaa7be48fdbf14836ff1bc61c72969960a5923c6.tar.xz linux-aaa7be48fdbf14836ff1bc61c72969960a5923c6.zip | |
MIPS: Probe for small (1KiB) page support
Probe Config3 for small page support. This will be useful to give clues
as to whether the PageGrain register exists.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10722/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index f25de771f7ed..9801ac982655 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -411,4 +411,8 @@ # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM) #endif +#ifndef cpu_has_small_pages +# define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP) +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 5fa7b8ba48a9..cd89e9855775 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -384,6 +384,7 @@ enum cpu_type_enum { #define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */ #define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */ #define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */ +#define MIPS_CPU_SP 0x10000000000ull /* Small (1KB) page support */ /* * CPU ASE encodings |