diff options
| author | Phil Sutter <n0-1@freewrt.org> | 2008-11-28 20:45:10 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-30 22:32:59 +0100 |
| commit | 4aa0f4d7264bc4f54603de5db1ffcaf8912ddd23 (patch) | |
| tree | ea927484cd34bbb9ac84e301e8d9ec469fe251b0 /arch/mips/include | |
| parent | MIPS: RC32434: Define io_map_base for PCI controller (diff) | |
| download | linux-4aa0f4d7264bc4f54603de5db1ffcaf8912ddd23.tar.xz linux-4aa0f4d7264bc4f54603de5db1ffcaf8912ddd23.zip | |
MIPS: RB532: Add set_type() function to IRQ struct.
Interrupt Group 4 mapps the GPIO pins enabled as interrupt sources;
add defines to make this clear when addressing them later in code.
The mapped GPIOs support triggering on either level high or low. To
achieve this, the set_type() function calls rb532_gpio_set_ilevel() for
interrupts of the above mentioned group.
As there is no way to alter the triggering characteristics of the other
interrupts, accept level triggering on status high only. (This is just a
guess; but as the system boots fine and interrupt-driven devices (e.g.
serial console) work with no implications, it seems to be right.)
To clear a GPIO mapped IRQ, the source has to be cleared (i.e., the
interrupt status bit of the corresponding GPIO pin). This is done inside
rb532_disable_irq().
After applying these changes I could undo most of my former "fixes" to
pata-rb532-cf. Particularly all interrupt handling can be done
generically via set_irq_type() as it was before.
Signed-off-by: Phil Sutter <n0-1@freewrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/mach-rc32434/irq.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h index 56738d8ec4e2..023a5b100ed0 100644 --- a/arch/mips/include/asm/mach-rc32434/irq.h +++ b/arch/mips/include/asm/mach-rc32434/irq.h @@ -30,4 +30,7 @@ #define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) #define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) +#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE +#define GPIO_MAPPED_IRQ_GROUP 4 + #endif /* __ASM_RC32434_IRQ_H */ |