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authorHillf Danton <dhillf@gmail.com>2011-11-16 01:21:29 +0100
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 23:04:57 +0100
commitb3ea581834c1e36cc76589e63dedcd99fd6abf51 (patch)
treefa32093d96a9b9469a0d2a39fdc169628db9981e /arch/mips/kernel/branch.c
parentMIPS: Netlogic: Add support for XLP 3XX cores (diff)
downloadlinux-b3ea581834c1e36cc76589e63dedcd99fd6abf51.tar.xz
linux-b3ea581834c1e36cc76589e63dedcd99fd6abf51.zip
MIPS: Netlogic: Mark Netlogic chips as SMT capable
Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. [jayachandranc: simplified and adapted for new merged XLR/XLP code] Signed-off-by: Hillf Danton <dhillf@gmail.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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