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author | Ralf Baechle <ralf@linux-mips.org> | 2005-05-31 13:49:19 +0200 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 20:31:17 +0200 |
commit | e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f (patch) | |
tree | 1928e8b0a4b7fb615e5a9f65dc934ba2e74cb9cd /arch/mips/kernel/branch.c | |
parent | 64-bit fixes for Alchemy code ;) (diff) | |
download | linux-e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f.tar.xz linux-e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f.zip |
Support the MIPS32 / MIPS64 DSP ASE.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/branch.c')
-rw-r--r-- | arch/mips/kernel/branch.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 56aea5f526a7..374de839558d 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -22,7 +22,7 @@ */ int __compute_return_epc(struct pt_regs *regs) { - unsigned int *addr, bit, fcr31; + unsigned int *addr, bit, fcr31, dspcontrol; long epc; union mips_instruction insn; @@ -99,6 +99,18 @@ int __compute_return_epc(struct pt_regs *regs) epc += 8; regs->cp0_epc = epc; break; + case bposge32_op: + if (!cpu_has_dsp) + goto sigill; + + dspcontrol = rddsp(0x01); + + if (dspcontrol >= 32) { + epc = epc + 4 + (insn.i_format.simmediate << 2); + } else + epc += 8; + regs->cp0_epc = epc; + break; } break; @@ -200,4 +212,9 @@ unaligned: printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; + +sigill: + printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); + force_sig(SIGBUS, current); + return -EFAULT; } |