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authorMarkos Chandras <markos.chandras@imgtec.com>2014-11-26 14:56:51 +0100
committerMarkos Chandras <markos.chandras@imgtec.com>2015-02-17 16:37:34 +0100
commit8467ca0122e20f3f8e73d34907b8b30461af5d4e (patch)
treeb2c543790a8035ff5bde5d8a93567459eca534c7 /arch/mips/kernel/branch.c
parentMIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions (diff)
downloadlinux-8467ca0122e20f3f8e73d34907b8b30461af5d4e.tar.xz
linux-8467ca0122e20f3f8e73d34907b8b30461af5d4e.zip
MIPS: Emulate the new MIPS R6 branch compact (BC) instruction
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/kernel/branch.c')
-rw-r--r--arch/mips/kernel/branch.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index cd880b91f092..1a0a30e16684 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -780,6 +780,15 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
epc += 8;
regs->cp0_epc = epc;
break;
+#else
+ case bc6_op:
+ /* Only valid for MIPS R6 */
+ if (!cpu_has_mips_r6) {
+ ret = -SIGILL;
+ break;
+ }
+ regs->cp0_epc += 8;
+ break;
#endif
}