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| author | Steven J. Hill <sjhill@mips.com> | 2012-08-31 23:18:49 +0200 |
|---|---|---|
| committer | Steven J. Hill <sjhill@mips.com> | 2012-09-13 22:43:49 +0200 |
| commit | 98b67c37db336446fa3a543654c012680bbe2291 (patch) | |
| tree | 53815c5db2034cf33de82364bea99302221f786f /arch/mips/kernel/cevt-r4k.c | |
| parent | MIPS: Code clean-ups for the GIC. (diff) | |
| download | linux-98b67c37db336446fa3a543654c012680bbe2291.tar.xz linux-98b67c37db336446fa3a543654c012680bbe2291.zip | |
MIPS: Add EIC support for GIC.
Add support to use an external interrupt controller with the GIC.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'arch/mips/kernel/cevt-r4k.c')
| -rw-r--r-- | arch/mips/kernel/cevt-r4k.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 51095dd9599d..75323925e537 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -15,6 +15,7 @@ #include <asm/smtc_ipi.h> #include <asm/time.h> #include <asm/cevt-r4k.h> +#include <asm/gic.h> /* * The SMTC Kernel for the 34K, 1004K, et. al. replaces several @@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev) */ static int c0_compare_int_pending(void) { +#ifdef CONFIG_IRQ_GIC + if (cpu_has_veic) + return gic_get_timer_pending(); +#endif return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); } |