diff options
| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2008-06-24 16:26:38 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-03 20:14:27 +0200 |
| commit | 8986d2f50e1a9ba63f64ccbf59181886aa7898c3 (patch) | |
| tree | 0fde3d8ff52cb4cac35348c2464939fc7b6fc9e9 /arch/mips/kernel/cevt-txx9.c | |
| parent | [MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES (diff) | |
| download | linux-8986d2f50e1a9ba63f64ccbf59181886aa7898c3.tar.xz linux-8986d2f50e1a9ba63f64ccbf59181886aa7898c3.zip | |
[MIPS] cevt-txx9: Reset timer counter on initialization
The txx9_tmr_init() will not clear a timer counter register in a certain
case. The counter register is cleared on 1->0 transition of TCE bit if
CRE=1. So just clearing the TCE bit is not enough.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cevt-txx9.c')
| -rw-r--r-- | arch/mips/kernel/cevt-txx9.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 795cb8fb0d74..b5fc4eb412d2 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr) struct txx9_tmr_reg __iomem *tmrptr; tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); + /* Start once to make CounterResetEnable effective */ + __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); + /* Stop and reset the counter */ __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); __raw_writel(0, &tmrptr->tisr); __raw_writel(0xffffffff, &tmrptr->cpra); |