diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-07-09 11:40:50 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-08-26 15:23:17 +0200 |
| commit | c982c6d6c48b48159db481581cadbb8773219677 (patch) | |
| tree | 78fdd17d2a30c16fb6a09cf709f01d22e2104c90 /arch/mips/kernel/cpu-probe.c | |
| parent | IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs (diff) | |
| download | linux-c982c6d6c48b48159db481581cadbb8773219677.tar.xz linux-c982c6d6c48b48159db481581cadbb8773219677.zip | |
MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB
We are so early in the boot process where we really don't want to
stall and wait for CP0 FTLB related changes become visible so just drop
the cp0 hazard barrier.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10649/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 02b75127dad3..dc057f37305b 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -385,7 +385,6 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) else /* Disable FTLB */ write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); - back_to_back_c0_hazard(); break; } } |