diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2019-05-08 00:43:56 +0200 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-07-22 00:23:23 +0200 |
| commit | 3b25b763116482596227225bea7c03fcde11c9ed (patch) | |
| tree | e7b3aa5066de745879645e748f8e38c912f05443 /arch/mips/kernel/cpu-probe.c | |
| parent | MIPS: Undefine PMD_ORDER for 32-bit builds (diff) | |
| download | linux-3b25b763116482596227225bea7c03fcde11c9ed.tar.xz linux-3b25b763116482596227225bea7c03fcde11c9ed.zip | |
MIPS: Rename JZRISC to XBURST
The real name of the CPU present in the JZ line of SoCs from Ingenic is
XBurst, not JZRISC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
[paul.burton@mips.com: Leave /proc/cpuinfo string as-is.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9635c1db3ae6..fd77dbc29af9 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1956,12 +1956,12 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); - /* JZRISC does not implement the CP0 counter. */ + /* XBurst does not implement the CP0 counter. */ c->options &= ~MIPS_CPU_COUNTER; BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); switch (c->processor_id & PRID_IMP_MASK) { - case PRID_IMP_JZRISC: - c->cputype = CPU_JZRISC; + case PRID_IMP_XBURST: + c->cputype = CPU_XBURST; c->writecombine = _CACHE_UNCACHED_ACCELERATED; __cpu_name[cpu] = "Ingenic JZRISC"; break; |