diff options
| author | Chris Dearman <chris@mips.com> | 2007-05-08 15:05:39 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 15:28:31 +0200 |
| commit | d725cf3818b12a17d78b87a2de19e8eec17126ae (patch) | |
| tree | 9d200020488b886201771bd6516c63ef43397baa /arch/mips/kernel/irq-msc01.c | |
| parent | [MIPS] Define and use vi_handler_t for vectored interrupt handlers. (diff) | |
| download | linux-d725cf3818b12a17d78b87a2de19e8eec17126ae.tar.xz linux-d725cf3818b12a17d78b87a2de19e8eec17126ae.zip | |
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq-msc01.c')
| -rw-r--r-- | arch/mips/kernel/irq-msc01.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 2967537221e2..410868b5ea5f 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = { }; -void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) +void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) { extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); - _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000); + _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); /* Reset interrupt controller - initialises all registers to 0 */ MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); @@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) switch (imp->im_type) { case MSC01_IRQ_EDGE: - set_irq_chip(base+n, &msc_edgeirq_type); + set_irq_chip(irqbase+n, &msc_edgeirq_type); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); else MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); break; case MSC01_IRQ_LEVEL: - set_irq_chip(base+n, &msc_levelirq_type); + set_irq_chip(irqbase+n, &msc_levelirq_type); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); else @@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) } } - irq_base = base; + irq_base = irqbase; MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ |