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author | Huacai Chen <chenhc@lemote.com> | 2018-09-05 11:33:01 +0200 |
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committer | Paul Burton <paul.burton@mips.com> | 2018-09-19 01:21:52 +0200 |
commit | c824ad164760484f709daa1339df40a184f4170a (patch) | |
tree | 9c824ca14aff39d91570f261a18a43f2603de7ec /arch/mips/kernel/machine_kexec.c | |
parent | MIPS/PCI: Call pcie_bus_configure_settings() to set MPS/MRRS (diff) | |
download | linux-c824ad164760484f709daa1339df40a184f4170a.tar.xz linux-c824ad164760484f709daa1339df40a184f4170a.zip |
MIPS: Loongson-3: Enable Store Fill Buffer at runtime
New Loongson-3 (Loongson-3A R2, Loongson-3A R3, and newer) has SFB
(Store Fill Buffer) which can improve the performance of memory access.
Now, SFB enablement is controlled by CONFIG_LOONGSON3_ENHANCEMENT, and
the generic kernel has no benefit from SFB (even it is running on a new
Loongson-3 machine). With this patch, we can enable SFB at runtime by
detecting the CPU type (the expense is war_io_reorder_wmb() will always
be a 'sync', which will hurt the performance of old Loongson-3).
[paul.burton@mips.com: Further info from Huacai:
In practise, I found that sometimes there are boot failures if I
enable SFB/LPA in cpu_probe(). I don't know why because processor
designers also haven't give me an explaination, but I think this may
have some relationships to speculative execution.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20426/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
Diffstat (limited to 'arch/mips/kernel/machine_kexec.c')
0 files changed, 0 insertions, 0 deletions