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authorAdam Buchbinder <adam.buchbinder@gmail.com>2016-02-25 09:44:58 +0100
committerRalf Baechle <ralf@linux-mips.org>2016-04-03 12:32:09 +0200
commit92a76f6d8545efc67f03278009e9a828bdad3419 (patch)
tree96929a7a5499d56640eaae43407db216cac69c1b /arch/mips/kernel/pm-cps.c
parentMIPS: tlb-r4k: panic if the MMU doesn't support PAGE_SIZE (diff)
downloadlinux-92a76f6d8545efc67f03278009e9a828bdad3419.tar.xz
linux-92a76f6d8545efc67f03278009e9a828bdad3419.zip
MIPS: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12617/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/pm-cps.c')
-rw-r--r--arch/mips/kernel/pm-cps.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index f63a289977cc..fa3f9ebad8f4 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
/*
* Disable all but self interventions. The load from COHCTL is defined
* by the interAptiv & proAptiv SUMs as ensuring that the operation
- * resulting from the preceeding store is complete.
+ * resulting from the preceding store is complete.
*/
uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);
uasm_i_sw(&p, t0, 0, r_pcohctl);