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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-12-12 20:44:25 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-12-12 20:44:25 +0100 |
| commit | 2bf3b685a35c80fe368dad9da0e77ba48b460939 (patch) | |
| tree | 3516a82ec33f96d5e9d3f36abef751aa0b788748 /arch/mips/kernel/ptrace.c | |
| parent | Documentation: intel_pstate: Document HWP energy/performance hints (diff) | |
| parent | cpufreq: schedutil: Rectify comment in sugov_irq_work() function (diff) | |
| download | linux-2bf3b685a35c80fe368dad9da0e77ba48b460939.tar.xz linux-2bf3b685a35c80fe368dad9da0e77ba48b460939.zip | |
Merge schedutil governor updates for v4.10.
Diffstat (limited to 'arch/mips/kernel/ptrace.c')
| -rw-r--r-- | arch/mips/kernel/ptrace.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 6103b24d1bfc..a92994d60e91 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -79,16 +79,15 @@ void ptrace_disable(struct task_struct *child) } /* - * Poke at FCSR according to its mask. Don't set the cause bits as - * this is currently not handled correctly in FP context restoration - * and will cause an oops if a corresponding enable bit is set. + * Poke at FCSR according to its mask. Set the Cause bits even + * if a corresponding Enable bit is set. This will be noticed at + * the time the thread is switched to and SIGFPE thrown accordingly. */ static void ptrace_setfcr31(struct task_struct *child, u32 value) { u32 fcr31; u32 mask; - value &= ~FPU_CSR_ALL_X; fcr31 = child->thread.fpu.fcr31; mask = boot_cpu_data.fpu_msk31; child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask); @@ -817,6 +816,7 @@ long arch_ptrace(struct task_struct *child, long request, break; #endif case FPC_CSR: + init_fp_ctx(child); ptrace_setfcr31(child, data); break; case DSP_BASE ... DSP_BASE + 5: { |