diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-12 00:45:58 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-12 00:45:58 +0200 |
| commit | d87d0c930a1591617e4c7c78296b4ba029150188 (patch) | |
| tree | 090902474c7df989d845da675508d0a8d7c4e7ae /arch/mips/kernel/smtc.c | |
| parent | [MIPS] vr41xx: add cpu_wait (diff) | |
| download | linux-d87d0c930a1591617e4c7c78296b4ba029150188.tar.xz linux-d87d0c930a1591617e4c7c78296b4ba029150188.zip | |
[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/smtc.c')
| -rw-r--r-- | arch/mips/kernel/smtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index fe22387d58b1..137183bba54f 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv) " addu %1, %0, 1 \n" " sc %1, %2 \n" " beqz %1, 1b \n" - " sync \n" + __WEAK_LLSC_MB : "=&r" (result), "=&r" (temp), "=m" (*pv) : "m" (*pv) : "memory"); |