diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-04 00:56:16 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 09:06:06 +0200 |
| commit | 875d43e72b5bf22161a81de7554f88eccf8a51ae (patch) | |
| tree | a676fe7298b478b7ee9fe7be9cb07c9a0b928370 /arch/mips/kernel/unaligned.c | |
| parent | [PATCH] mips: changed from VR41xx to VR4100 series in Kconfig (diff) | |
| download | linux-875d43e72b5bf22161a81de7554f88eccf8a51ae.tar.xz linux-875d43e72b5bf22161a81de7554f88eccf8a51ae.zip | |
[PATCH] mips: clean up 32/64-bit configuration
Start cleaning 32-bit vs. 64-bit configuration.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/mips/kernel/unaligned.c')
| -rw-r--r-- | arch/mips/kernel/unaligned.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 3f24a1d45865..36c5212e0928 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -240,7 +240,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, break; case lwu_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -278,13 +278,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, *newvalue = value; *regptr = ®s->regs[insn.i_format.rt]; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; case ld_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -320,7 +320,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, *newvalue = value; *regptr = ®s->regs[insn.i_format.rt]; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; @@ -392,7 +392,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, break; case sd_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -428,7 +428,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, if (res) goto fault; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; |