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| author | Thomas Gleixner <tglx@linutronix.de> | 2007-08-28 11:03:01 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-12 00:46:02 +0200 |
| commit | 4e45171c4e31578157189ca22cfb7b2bcc5f69f2 (patch) | |
| tree | 2b5d3dea2f711e0a138496ff8659b8da80d7bd6d /arch/mips/kernel | |
| parent | [MIPS] Add support for BCM47XX CPUs. (diff) | |
| download | linux-4e45171c4e31578157189ca22cfb7b2bcc5f69f2.tar.xz linux-4e45171c4e31578157189ca22cfb7b2bcc5f69f2.zip | |
[MIPS] cleanup struct irqaction initializers
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
CC: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/i8259.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 4f4359bfd180..60021647cac1 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -303,7 +303,9 @@ void init_8259A(int auto_eoi) * IRQ2 is cascade interrupt to second interrupt controller */ static struct irqaction irq2 = { - no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", }; static struct resource pic1_io_resource = { |