diff options
| author | Steven J. Hill <Steven.Hill@imgtec.com> | 2013-06-05 23:25:17 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-07-01 15:10:58 +0200 |
| commit | c6213c6c9c189aeb97010673e3129a8929d2223e (patch) | |
| tree | 1b0eb42862e8b71accb5d2a0021400eea99d79a6 /arch/mips/kernel | |
| parent | MIPS: Don't try to decode microMIPS branch instructions where they cannot exist. (diff) | |
| download | linux-c6213c6c9c189aeb97010673e3129a8929d2223e.tar.xz linux-c6213c6c9c189aeb97010673e3129a8929d2223e.zip | |
MIPS: microMIPS: Fix improper definition of ISA exception bit.
The ISA exception bit selects whether exceptions are taken in classic
or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
defined as bits 16 and 17 instead of just bit 16. A new function was
added so that platforms could set this bit when running a kernel
compiled with only microMIPS instructions.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5377/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 3 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 9 |
2 files changed, 9 insertions, 3 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f87039dbefe9..c7b1b3c5a761 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -269,9 +269,6 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_ISA) c->options |= MIPS_CPU_MICROMIPS; -#ifdef CONFIG_CPU_MICROMIPS - write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE); -#endif if (config3 & MIPS_CONF3_VZ) c->ases |= MIPS_ASE_VZ; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d97ea234e2d3..b0f3ad26063e 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1878,6 +1878,15 @@ void __init trap_init(void) ebase += (read_c0_ebase() & 0x3ffff000); } + if (cpu_has_mmips) { + unsigned int config3 = read_c0_config3(); + + if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) + write_c0_config3(config3 | MIPS_CONF3_ISA_OE); + else + write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); + } + if (board_ebase_setup) board_ebase_setup(); per_cpu_trap_init(true); |