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| author | James Hogan <james.hogan@imgtec.com> | 2017-03-14 11:25:46 +0100 |
|---|---|---|
| committer | James Hogan <james.hogan@imgtec.com> | 2017-03-28 16:36:17 +0200 |
| commit | 1c506c9c104cf01d01a9633ad2e76f15f938c54c (patch) | |
| tree | 27df069d8a6e31f4c76f4bfb18790727ae3d50c7 /arch/mips/kvm/trap_emul.c | |
| parent | KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon (diff) | |
| download | linux-1c506c9c104cf01d01a9633ad2e76f15f938c54c.tar.xz linux-1c506c9c104cf01d01a9633ad2e76f15f938c54c.zip | |
KVM: MIPS/TLB: Handle virtually tagged icaches
When TLB entries are invalidated in the presence of a virtually tagged
icache, such as that found on Octeon CPUs, flush the icache so that we
don't get a reserved instruction exception even though the TLB mapping
is removed.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Diffstat (limited to 'arch/mips/kvm/trap_emul.c')
0 files changed, 0 insertions, 0 deletions