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| author | John Crispin <blogic@openwrt.org> | 2013-01-19 09:54:25 +0100 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-02-17 00:15:17 +0100 |
| commit | d0c550dc36881fda171ec8ad3dcc67491ad968eb (patch) | |
| tree | 2d086dea11edbdd0eb1bc5c1819147445cd6f126 /arch/mips/lantiq/xway/sysctrl.c | |
| parent | MIPS: lantiq: adds static clock for PP32 (diff) | |
| download | linux-d0c550dc36881fda171ec8ad3dcc67491ad968eb.tar.xz linux-d0c550dc36881fda171ec8ad3dcc67491ad968eb.zip | |
MIPS: lantiq: add GPHY clock gate bits
Explicitly enable the clock gate of the internal GPHYs found on xrx200.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/
Diffstat (limited to 'arch/mips/lantiq/xway/sysctrl.c')
| -rw-r--r-- | arch/mips/lantiq/xway/sysctrl.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 3390fcd6ee56..c24924fe087d 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -376,6 +376,7 @@ void __init ltq_soc_init(void) PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | PMU_PPE_QSB | PMU_PPE_TOP); + clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY); } else if (of_machine_is_compatible("lantiq,ar9")) { clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), ltq_ar9_fpi_hz(), CLOCK_250M); |