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| author | Ralf Baechle <ralf@linux-mips.org> | 2016-08-03 12:55:49 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-08-03 12:55:49 +0200 |
| commit | 4a89cf810130fde41e3fc729e770cb1a5a87d245 (patch) | |
| tree | 84da40f8d26e51c21e61fc4fc5b7242c0050ae7d /arch/mips/lantiq | |
| parent | MIPS: mm: Fix definition of R6 cache instruction (diff) | |
| parent | MIPS: Fix MSA asm warnings in control reg accessors (diff) | |
| download | linux-4a89cf810130fde41e3fc729e770cb1a5a87d245.tar.xz linux-4a89cf810130fde41e3fc729e770cb1a5a87d245.zip | |
Merge branch '4.7-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/lantiq')
| -rw-r--r-- | arch/mips/lantiq/irq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index ac4f2fa7ccef..8ac0e5994ed2 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -344,7 +344,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) if (hw == ltq_eiu_irq[i]) chip = <q_eiu_type; - irq_set_chip_and_handler(hw, chip, handle_level_irq); + irq_set_chip_and_handler(irq, chip, handle_level_irq); return 0; } |