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authorRalf Baechle <ralf@linux-mips.org>2012-10-05 15:56:28 +0200
committerRalf Baechle <ralf@linux-mips.org>2012-10-05 15:56:28 +0200
commit382fc33b4a04e2dde89b4c69a6880e0c7d9761e2 (patch)
tree9d13ef333c4e841756c45bf29600ceac28e3f85e /arch/mips/lantiq
parentMIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs (diff)
parentMIPS: BCM63XX: remove bogus ENETSW_TXDMA interrupts from BCM6328 (diff)
downloadlinux-382fc33b4a04e2dde89b4c69a6880e0c7d9761e2.tar.xz
linux-382fc33b4a04e2dde89b4c69a6880e0c7d9761e2.zip
Merge branch 'master' of git://dev.phrozen.org/mips-next into mips-for-linux-next
Diffstat (limited to 'arch/mips/lantiq')
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 67c3a91e54e7..2917b56b6b25 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -188,10 +188,12 @@ static int clkout_enable(struct clk *clk)
for (i = 0; i < 4; i++) {
if (clk->rates[i] == clk->rate) {
int shift = 14 - (2 * clk->module);
+ int enable = 7 - clk->module;
unsigned int val = ltq_cgu_r32(ifccr);
val &= ~(3 << shift);
val |= i << shift;
+ val |= enable;
ltq_cgu_w32(val, ifccr);
return 0;
}